Proposal title:

Enhanced Performance CMOS Phase-locked Loop Synthesizer (project code: Τ2ΕΔΚ-02322)


Operational Program «Competitiveness, Entrepreneurship and Innovation», under the call RESEARCH – CREATE – INNOVATE


The subject of the project is the design of an integrated circuit, the implementation of a prototype in silicon and its experimental verification. It includes the development of a phase locked loop (PLL) and the associated oscillator, capable of high resolution frequency synthesis, operating in the 8.5-11.5GHz frequency range. The PLL is being designed so that it can cover a very wide range of telecommunication applications. Its specifications are such as to satisfy demanding application fields in terms of phase noise, frequency analysis, power consumption, lock time, etc. The resulting silicon IP can be integrated into a large number of telecommunication systems such as 5G, satellite, backhaul , RADAR, Backhaul, etc.

Total budget:

Total budget: 281.517€ (public expenditure: 225.214€)


17 months (started: 01/01/2020)